The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density has generally increased while feature size has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. One method used by the industry to meet the demands for device density is the adoption of damascene and dual-damascene structures for interconnect structures. In a typical damascene process, an underlying insulating layer is patterned with open trenches where the conductor is then deposited and polished to the level of the insulating layer to form a patterned conductor feature. Dual-damascene processes consider a similar approach and generally form and fill two features (a trench and a via) with a single deposition of conductor.
However, as the feature sizes further shrink and density requirements increase, the pitch of features such as interconnect structures decrease. This can cause tension between the overlay specification window and critical dimensions (e.g., of a via of a dual damascene structure). For example, the via size may be such that it is larger than the associated metal feature or trench. This may cause defects that can affect process yields, such as via-induced-metal-bridge (VIMB) or leakage defects. Other tension that can arise with the decreasing feature size and increasing density is the ability to provide a corresponding interconnect pitch. One approach used to facilitate the small pitch is a two-photolithography, two-etch (2P2E) approach which can provide the appropriate lithography depth of focus (DOF). However, the process may be complicated and cost-inducing.
Accordingly, what is needed is a method for fabricating an IC device that addresses one or more of the above stated issues.